LSI 53C875A Manual do Utilizador

®S14047LSI53C875APCI to Ultra SCSIControllerTECHNICALMANUALDecember 2000Version 2.0

xContents6.3 AC Characteristics 6-96.4 PCI and External Memory Interface Timing Diagrams 6-116.4.1 Target Timing 6-136.4.2 Initiator Timing 6-196.4.3

4-8 RegistersRegister: 0x0DLatency TimerRead/WriteLT Latency Timer [7:0]The Latency Timer register specifies, in units of PCI busclocks, the value of

PCI Configuration Registers 4-9Registers:0x10–0x13Base Address Register Zero (I/O)Read/WriteBAR0 Base Address Register Zero - I/O [31:0]This base addr

4-10 RegistersRegisters:0x18–0x1BBase Address Register Two (SCRIPTS RAM)Read/WriteBAR2 Base Address Register Two [31:0]This base register is used to m

PCI Configuration Registers 4-11controller installed on them (and therefore the sameVendor ID and Device ID).If the external serial EEPROM interface i

4-12 Registersvalue that should be stored in the external serialEEPROM is vendor specific. Please see the Section 2.4“Serial EEPROM Interface” in Chap

PCI Configuration Registers 4-13Register: 0x34Capabilities PointerRead OnlyCP Capabilities Pointer [7:0]This register indicates that the first extende

4-14 RegistersRegister: 0x3DInterrupt PinRead OnlyIP Interrupt Pin [7:0]This register indicates which interrupt pin the deviceuses. Its value is set t

PCI Configuration Registers 4-15Register: 0x40Capability IDRead OnlyCID Cap_ID [7:0]This register indicates the type of data structure currentlybeing

4-16 RegistersD2S D2_Support 10The LSI53C875A sets this bit to indicate support forpower management state D2.D1S D1_Support 9The LSI53C875A sets this

PCI Configuration Registers 4-17DSCL Data_Scale [14:13]The LSI53C875A does not support the data register.Therefore, these two bits are always cleared.

Contents xi6.9 PCI Configuration Register Read 6-136.10 PCI Configuration Register Write 6-146.11 32-Bit Operating Register/SCRIPTS RAM Read 6-156.12

4-18 RegistersRegister: 0x47DataRead OnlyDATA Data [7:0]This register provides an optional mechanism for thefunction to report state-dependent operati

SCSI Registers 4-19Table 4.2 SCSI Register Address Map31 16 15 0SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00GPREG0 SDID SXFER SCID 0x04SBCL SSID SOCL SFBR 0x08SST

4-20 RegistersRegister: 0x00SCSI Control Zero (SCNTL0)Read/WriteARB[1:0] Arbitration Mode Bits 1 and 0 [7:6]Simple Arbitration1. The LSI53C875A waits

SCSI Registers 4-21Full Arbitration, Selection/Reselection1. The LSI53C875A waits for a bus free condition.2. It asserts SBSY/ and its SCSI ID (the hi

4-22 RegistersWATN Select with SATN/ on a Start Sequence 4When this bit is set and the LSI53C875A is in the initiatormode, the SATN/ signal is asserte

SCSI Registers 4-23(SET TARGET or CLEAR TARGET). When this bit is set, thechip is a target device by default. When this bit is cleared,the LSI53C875A

4-24 Registersmay transfer up to three additional bytes before halting tosynchronize between internal core cells. Duringsynchronous operation, the LSI

SCSI Registers 4-25SCSI Control Zero (SCNTL0) register are set for fullarbitration and selection before setting this bit.Arbitration is retried until

4-26 RegistersCaution: Writing to this register while not connected may cause theloss of a selection/reselection by clearing the Connectedbit.Register

SCSI Registers 4-27combined with the first byte from the subsequent transferso that a wide transfer is completed.SLPMD SLPAR Mode 5If this bit is clea

xii ContentsB.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 MbyteInterface with 150 ns Memory B-3B.4 512 Kbyte Interface with 150 ns Memory B-4Tables2.1

4-28 Registersgroup codes. If this bit is set, the device does not reloadthe Block Move byte count, regardless of the group code.WSR Wide SCSI Receive

SCSI Registers 4-29SCF[2:0] Synchronous Clock Conversion Factor [6:4]These bits select a factor by which the frequency ofSCLK is divided before being

4-30 RegistersRegister: 0x04SCSI Chip ID (SCID)Read/WriteR Reserved 7RRE Enable Response to Reselection 6When this bit is set, the LSI53C875A is enabl

SCSI Registers 4-31Register: 0x05SCSI Transfer (SXFER)Read/WriteNote:When using Table Indirect I/O commands, bits [7:0] of thisregister are loaded fro

4-32 Registers(This SCSI synchronous core clock is determined inSCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is assertedand the LSI53C875A is sending

SCSI Registers 4-33Table 4.4 shows example transfer periods and rates for fast SCSI-2 andUltra SCSI.MO[4:0] Max SCSI Synchronous Offset [4:0]These bit

4-34 RegistersTable 4.5 Maximum Synchronous OffsetMO4 MO3 MO2 MO1 MO0 Synchronous Offset00000 0-Asynchronous00001 100010 200011 300100 400101 500110 6

SCSI Registers 4-35Register: 0x06SCSI Destination ID (SDID)Read/WriteR Reserved [7:4]ENC Encoded Destination SCSI ID [3:0]Writing these bits set the S

4-36 Registersis also possible to program these signals as live inputsand sense them through a SCRIPTS register to registerMove Instruction. GPIO4 may

SCSI Registers 4-37abytestoredinsystemmemory,thebytemustfirstbemoved to an intermediate LSI53C875A register (such asa SCRATCH register), and then to t

Contents xiii5.2 SCSI Information Transfer Phase 5-125.3 Read/Write Instructions 5-245.4 Transfer Control Instructions 5-265.5 SCSI Phase Comparisons

4-38 RegistersRegister: 0x0ASCSI Selector ID (SSID)Read OnlyVAL SCSI Valid 7If VAL is asserted, then the two SCSI IDs are detectedon the bus during a

SCSI Registers 4-39REQ SREQ/ Status 7ACK SACK/ Status 6BSY SBSY/ Status 5SEL SSEL/ Status 4ATN SATN/ Status 3MSG SMSG/ Status 2C_D SC_D/ Status 1I_O S

4-40 RegistersMDPE Master Data Parity Error 6This bit is set when the LSI53C875A as a master detectsa data parity error, or a target device signals a

SCSI Registers 4-41• During a Transfer Control instruction, the CompareData (bit 18) and Compare Phase (bit 17) bits are setin the DMA Byte Counter (D

4-42 RegistersRegister: 0x0DSCSI Status Zero (SSTAT0)Read OnlyILF SIDL Least Significant Byte Full 7This bit is set when the least significant byte in

SCSI Registers 4-43AIP Arbitration in Progress 4Arbitration in Progress (AIP = 1) indicates that theLSI53C875A has detected a Bus Free condition, asse

4-44 Registerssynchronous data transfers, or up to 31 words for wide.Values over 31 will not occur.Table 4.6 SCSI Synchronous Data FIFO Word CountFF4(

SCSI Registers 4-45SDP0L Latched SCSI Parity 3This bit reflects the SCSI parity signal (SDP0/),corresponding to the data latched in the SCSI Input Dat

4-46 RegistersRegister: 0x0FSCSI Status Two (SSTAT2)Read OnlyILF1 SIDL Most Significant Byte Full 7This bit is set when the most significant byte in t

SCSI Registers 4-47field, see the definition for SCSI Status One (SSTAT1)bits [7:4].SPL1 Latched SCSI Parity for SD[15:8] 3This active HIGH bit reflec

xiv Contents6.30 External Memory Write 6-386.31 Normal/Fast Memory (≥ 128 Kbytes) Single ByteAccess Read Cycle 6-426.32 Normal/Fast Memory (≥ 128 Kbyt

4-48 RegistersRegister: 0x14Interrupt Status Zero (ISTAT0)Read/WriteThis register is accessible by the host CPU while a LSI53C875A isexecuting SCRIPTS

SCSI Registers 4-49clear the ID Mode bit or any of the PCI configurationregisters. This bit is not self-clearing; it must be clearedto clear the reset

4-50 Registersthe SCRIPTS processor is still executing a SCRIPTSprogram. If this bit is set when the Interrupt Status Zero(ISTAT0) or Interrupt Status

SCSI Registers 4-51• A bus fault is detected• An abort condition is detected• A SCRIPTS instruction is executed in single stepmode• A SCRIPTS interrup

4-52 Registersaddition, this bit may be read and written while SCRIPTSare executing.Register: 0x16Mailbox Zero (MBOX0)Read/WriteMBOX0 Mailbox Zero [7:

SCSI Registers 4-53Register: 0x18Chip Test Zero (CTEST0)Read/WriteFMT Byte Empty in DMA FIFO [7:0]These bits identify the bottom bytes in the DMA FIFO

4-54 RegistersRegister: 0x1AChip Test Two (CTEST2)Read Only (bit 3 write)DDIR Data Transfer Direction 7This status bit indicates which direction data

SCSI Registers 4-55Base Address Register One (MEMORY).Thisisthememory mapped operating register base address. Bits[9:0] will be 0. The SCRATCHB regist

4-56 RegistersRegister: 0x1BChip Test Three (CTEST3)Read/WriteV ChipRevisionLevel [7:4]These bits identify the chip revision level for softwarepurpose

SCSI Registers 4-57WRIE Write and Invalidate Enable 0This bit, when set, causes the issuing of Write andInvalidate commands on the PCI bus whenever le

LSI53C875A PCI to Ultra SCSI Controller 1-1Chapter 1General DescriptionChapter 1 is divided into the following sections:• Section 1.1, “New Features i

4-58 Registerswhile data is being transferred between the two cores.Once the chip has stopped transferring data, these bitsare stable.The DMA FIFO (DF

SCSI Registers 4-59Register: 0x21Chip Test Four (CTEST4)Read/WriteBDIS Burst Disable 7When set, this bit causes the LSI53C875A to performback-to-back

4-60 RegistersLSI53C875A is informed of the error by the PERR/ pinbeing asserted by the target. When this bit is cleared, theLSI53C875A does not inter

SCSI Registers 4-61the current DBC value. This bit automatically clears itselfafter incrementing the DNAD register.BBCK Clock Byte Counter 6Setting th

4-62 RegistersBO[9:8] DMA FIFO Byte Offset Counter, Bits [9:8] [1:0]These are the upper two bits of the DFBOC. The DFBOCconsists of these bits, and th

SCSI Registers 4-63LSI53C875A. The DBC counter is decremented eachtime data is transferred on the PCI bus. It is decrementedby an amount equal to the

4-64 RegistersRegisters:0x28–0x2BDMA Next Address (DNAD)Read/WriteDNAD DMA Next Address [31:0]This 32-bit register contains the general purpose addres

SCSI Registers 4-65Registers:0x30–0x33DMA SCRIPTS Pointer Save (DSPS)Read/WriteDSPS DMA SCRIPTS Pointer Save [31:0]This register contains the second D

4-66 RegistersRegister: 0x38DMA Mode (DMODE)Read/WriteBL[1:0] Burst Length [7:6]These bits control the maximum number of Dwordstransferred per bus own

SCSI Registers 4-67SIOM Source I/O Memory Enable 5This bit is defined as an I/O Memory Enable bit for thesource address of a Memory Move or Block Move

1-2 General DescriptionFigure 1.1 Typical LSI53C875A System ApplicationFigure 1.2 Typical LSI53C875A Board ApplicationPCI BusInterfaceControllerLSI53C

4-68 RegistersERMP Enable Read Multiple 2If this bit is set and cache mode is enabled, a ReadMultiple command is used on all read cycles when it isleg

SCSI Registers 4-69Register: 0x39DMA Interrupt Enable (DIEN)Read/WriteR Reserved 7MDPE Master Data Parity Error 6BF Bus Fault 5ABRT Aborted 4SSI Singl

4-70 RegistersFor more information on interrupts, see Chapter 2, “FunctionalDescription”.Register: 0x3AScratch Byte Register (SBR)Read/WriteSBR Scratc

SCSI Registers 4-71the LSI53C875A to make more efficient use of thesystem PCI bus, thus improving overall systemperformance. The unit will flush whene

4-72 RegistersSTD Start DMA Operation 2The LSI53C875A fetches a SCSI SCRIPTS instructionfrom the address contained in the DMA SCRIPTS Pointer(DSP) reg

SCSI Registers 4-73Registers:0x3C–0x3FAdder Sum Output (ADDER)Read OnlyADDER Adder Sum Output [31:0]This register contains the output of the internal

4-74 RegistersCMP Function Complete 6Indicates full arbitration and selection sequence iscompleted.SEL Selected 5Indicates the LSI53C875A is selected

SCSI Registers 4-75RST SCSI Reset Condition 1Indicates assertion of the SRST/ signal by theLSI53C875A or any other SCSI device. This condition isedge-

4-76 RegistersHTH Handshake-to-Handshake Timer Expired 0The handshake-to-handshake timer is expired. The timemeasured is the SCSI Request-to-Request (

SCSI Registers 4-77target. In target mode, this bit is set when the SATN/signal is asserted by the initiator.CMP Function Complete 6This bit is set wh

New Features in the LSI53C875A 1-31.1 New Features in the LSI53C875AThe LSI53C875A is a drop-in replacement for the LSI53C875 PCI toUltra SCSI Control

4-78 Registers• Residual data in the synchronous data FIFO – atransfer other than synchronous data receive isstarted with data left in the synchronous

SCSI Registers 4-79(SIEN1) register or not. Each bit that is set indicates an occurrence ofthe corresponding condition.Reading the SIST1 clears the in

4-80 Registerscheck byte are received from the SCSI bus (all signalsare shown active HIGH):A one in any bit position of the final SLPAR value wouldind

SCSI Registers 4-81WhichbyteisaccessediscontrolledbytheSLPHBENbitin the SCSI Control Two (SCNTL2) register.Register: 0x45SCSI Wide Residue (SWIDE)Read

4-82 RegistersDWR Data Write 3This bit is used to define if a data write is considered tobe a local memory access.DRD Data Read 2This bit is used to d

SCSI Registers 4-83LEDC LED_CNTL 5The internal connected signal (bit 3 of the Interrupt StatusZero (ISTAT0) register) will be presented on GPIO0 if th

4-84 RegistersSEL[3:0] Selection Time-Out [3:0]These bits select the SCSI selection/reselection time-outperiod. When this timing (plus the 200µs selec

SCSI Registers 4-85Register: 0x49SCSI Timer One (STIME1)Read/WriteR Reserved 7HTHBA Handshake-to-Handshake Timer Bus ActivityEnable 6Setting this bit

4-86 RegistersRegister: 0x4AResponse ID Zero (RESPID0)Read/WriteRESPIO0 Response ID Zero [7:0]RESPID0 and Response ID One (RESPID1) contain theselecti

SCSI Registers 4-87chipcanarbitratewithonlyoneIDvalueintheSCIDregister.Register: 0x4CSCSI Test Zero (STEST0)Read OnlySSAID SCSI Selected As ID [7:4]Th

1-4 General Descriptionsynchronous negotiations for Ultra SCSI rates and to enable the clockquadrupler. Chapter 2, “Functional Description,” contains

4-88 RegistersSOM SCSI Synchronous Offset Maximum 0This bit indicates that the current synchronous SREQ/,SACK/ offset is the maximum specified by bits

SCSI Registers 4-89QSEL SCLK Quadrupler Select 2This bit, when set, selects the output of the internal clockquadrupler for use as the internal SCSI cl

4-90 RegistersSZM SCSI High Impedance Mode 3Setting this bit places all the open drain 48 mA SCSIdrivers into a high impedance state. This is to allow

SCSI Registers 4-91Register: 0x4FSCSI Test Three (STEST3)Read/WriteTE TolerANT Enable 7Setting this bit enables the active negation portion ofLSI Logi

4-92 Registersfor test purposes or to lower IDDduring a power-downmode.DSI Disable Single Initiator Response 4If this bit is set, the LSI53C875A ignor

SCSI Registers 4-93STW SCSI FIFO Test Write 0Setting this bit places the SCSI core into a test mode inwhich the FIFO is easily read or written. While

4-94 RegistersRegister: 0x52SCSI Test Four (STEST4)Read OnlyR Reserved [7:6]LOCK Frequency Lock 5This bit is used when enabling the SCSI clock quadrup

SCSI Registers 4-95Register: 0x56Chip Control 0 (CCNTL0)Read/WriteENPMJ Enable Phase Mismatch Jump 7Upon setting this bit, any phase mismatches do not

4-96 RegistersENNDJ Enable Jump on Nondata Phase Mismatches 5This bit controls whether or not a jump is taken during anondata phase mismatch (i.e. mes

SCSI Registers 4-97Register: 0x57Chip Control 1 (CCNTL1)Read/WriteZMODE High Impedance Mode 7Setting this bit causes the LSI53C875A to place all outpu

LSI53C875A Benefits Summary 1-5• Ease of Use• Flexibility• Reliability• Testability1.4.1 SCSI PerformanceTo improve SCSI performance, the LSI53C875A:•

4-98 RegistersIndex Mode 1 (64TIMOD set) table entry format:EN64TIBMV Enable 64-Bit Table Indirect BMOV 1Setting this bit enables 64-bit addressing fo

64-Bit SCRIPTS Selectors 4-99Register: 0x5A–0x5BReservedRegisters:0x5C–0x5FScratch Register B (SCRATCHB)Read/WriteSCRATCHB Scratch Register B [31:0]Th

4-100 Registersoperation is performed, one of the six selector registers below will beused to generate a 64-bit address.If the selector for a particul

64-Bit SCRIPTS Selectors 4-101Registers:0xA4–0xA7Memory Move Write Selector (MMWS)Read/WriteMMWS Memory Move Write Selector [31:0]Supplies the upper D

4-102 RegistersWrites to the SFS register are unaffected. Clearing thePCI Configuration Into Enable bit causes the SFS registerto return to normal ope

Phase Mismatch Jump Registers 4-103Registers:0xB4–0xB7Dynamic Block Move Selector (DBMS)Read/WriteDBMS Dynamic Block Move Selector [31:0]Supplies the

4-104 RegistersRegisters:0xC0–0xC3PhaseMismatchJumpAddress1(PMJAD1)Read/WritePMJAD1 Phase Mismatch Jump Address 1 [31:0]This register contains the 32-

Phase Mismatch Jump Registers 4-105Registers:0xC8–0xCBRemaining Byte Count (RBC)Read/WriteRBC Remaining Byte Count (RBC) [31:0]This register contains

4-106 RegistersIn the case of a SCSI data receive, if there is a byte inthe SCSI Wide Residue (SWIDE) register then thisaddress will point to the loca

Phase Mismatch Jump Registers 4-107Registers:0xD4–0xD7Instruction Address (IA)Read/WriteIA Instruction Address [31:0]This register always contains the

iiThis document contains proprietary information of LSI Logic Corporation. Theinformation contained herein is not to be used by or disclosed to third

1-6 General Description• Supports additional arithmetic capability with the Expanded RegisterMove instruction.1.4.2 PCI PerformanceTo improve PCI perf

4-108 Registerscannot be counted for this BMOV as it was actually partof the byte count for the previous BMOV.Register: 0xDBReservedRegisters:0xDC–0xD

LSI53C875A PCI to Ultra SCSI Controller 5-1Chapter 5SCSI SCRIPTSInstruction SetThe LSI53C875A contains a SCSI SCRIPTS processor that permits bothDMA a

5-2 SCSI SCRIPTS Instruction Setrequire certain unique timings or bus sequences to operate properly.Another feature allowed at the low level is loopba

High Level SCSI SCRIPTS Mode 5-3Each instruction consists of two or three 32-bit words. The first 32-bitword is always loaded into the DMA Command (DC

5-4 SCSI SCRIPTS Instruction Set• The LSI53C875A typically fetches two Dwords (64 bits) and decodesthe high order byte of the first longword as a SCRI

High Level SCSI SCRIPTS Mode 5-5Figure 5.1 SCRIPTS OverviewSystem ProcessorSystem MemorySCSI Initiator Write Example× Select ATN 0, alt_addr× Move fro

5-6 SCSI SCRIPTS Instruction Set5.3 Block Move InstructionPerforming a Block Move instruction, bit 5, Source I/O - Memory Enable(SIOM) and bit 4, Dest

Block Move Instruction 5-7Direct AddressingThe byte count and absolute address are:Indirect AddressingUse the fetched byte count, but fetch the data a

5-8 SCSI SCRIPTS Instruction Setthe data structure. Sign extended values of all ones fornegative values are allowed, but bits [31:24] are ignored.Note

Block Move Instruction 5-9OPC OpCode 27This 1-bit OpCode field defines the type of Block Move(MOVE) Instruction to be preformed in Target and Initiato

LSI53C875A Benefits Summary 1-7• Up to one megabyte of add-in memory support for BIOS andSCRIPTS storage.• Reduced SCSI development effort.• Compiler-

5-10 SCSI SCRIPTS Instruction Setregister contains 0x000000, an illegal instructioninterrupt is generated.4. The LSI53C875A transfers the number of by

Block Move Instruction 5-11register. These phase lines are latched when SREQ/ isasserted.4. IftheSCSIphasebitsmatchthevaluestoredintheSCSISCSI Status

5-12 SCSI SCRIPTS Instruction SetTC[23:0] Transfer Counter [23:0]This 24-bit field specifies the number of data bytes to bemoved between the LSI53C875

I/O Instruction 5-135.3.2 Second DwordStart Address [31:0]This 32-bit field specifies the starting address of the datato move to/from memory. This fie

5-14 SCSI SCRIPTS Instruction Set5.4.1 First DwordIT[1:0] Instruction Type - I/O Instruction [31:30]The IT bit configuration (01) defines an I/O Instr

I/O Instruction 5-15This way the SCRIPTS can move on to the nextinstruction before the reselection completes. It continuesexecuting SCRIPTS until a SC

5-16 SCSI SCRIPTS Instruction SetWhen the SACK/ or SATN/ bits are cleared, thecorresponding bits are cleared in theSCSI Output Control Latch (SOCL) re

I/O Instruction 5-17the LSI53C875A to Initiator mode if it is reselected, or toTarget mode if it is selected.If the Select with SATN/ field is set, th

5-18 SCSI SCRIPTS Instruction SetRA Relative Addressing Mode 26When this bit is set, the 24-bit signed value in the DMANext Address (DNAD) register is

I/O Instruction 5-19Use this bit only in conjunction with the Select, Reselect,Wait Select, and Wait Reselect instructions. Use bits 25and 26 individu

1-8 General Description• SCSI clock quadrupler bits enable Ultra SCSI transfer rates with a 20or 40 MHz SCSI clock input.• Selectable IRQ pin disable

5-20 SCSI SCRIPTS Instruction SetTable RelativeTreats the alternate jump address as a relative jump andfetches the device ID, synchronous offset, ands

I/O Instruction 5-21R Reserved [8:7]ACK Set/Clear SACK/ 6R Reserved [5:4]ATN Set/Clear SATN/ 3These two bits are used in conjunction with a Set or Cle

5-22 SCSI SCRIPTS Instruction SetIf relative or table relative addressing is used, this valueis a 24-bit signed offset relative to the current DMASCRI

Read/Write Instructions 5-23A[6:0] Register Address - A[6:0] [22:16]It is possible to change register values from SCRIPTS inread-modify-write cycles o

5-24 SCSI SCRIPTS Instruction Set5.5.4 Move To/From SFBR CyclesAll operations are read-modify-writes. However, two registers areinvolved, one of which

Transfer Control Instructions 5-25Miscellaneous Notes:• Substitute the desired register name or address for “RegA” in the syntax examples.• data8 indi

5-26 SCSI SCRIPTS Instruction Set5.6.1 First DwordIT[1:0] Instruction Type - Transfer ControlInstruction [31:30]The IT bit configuration (10) defines

Transfer Control Instructions 5-27DMA SCRIPTS Pointer Save (DSPS) register. The DSPregister now contains the address of the next instruction.If the co

5-28 SCSI SCRIPTS Instruction SetIf the comparisons are false, the LSI53C875A fetches thenext instruction from the address pointed to by the DSPregist

Transfer Control Instructions 5-29RA Relative Addressing Mode 23When this bit is set, the 24-bit signed value in the DMASCRIPTS Pointer Save (DSPS) re

LSI53C875A PCI to Ultra SCSI Controller 2-1Chapter 2Functional DescriptionChapter 2 is divided into the following sections:• Section 2.1, “PCI Functio

5-30 SCSI SCRIPTS Instruction Setsigned (2’s complement), the jump can be forward orbackward.A relative transfer can be to any address within a16 Mbyt

Transfer Control Instructions 5-31CD Compare Data 18When this bit is set, the first byte received from the SCSIdata bus (contained in the SCSI First B

5-32 SCSI SCRIPTS Instruction SetDCV Data Compare Value [7:0]This 8-bit field is the data compared against the register.These bits are used in conjunc

Memory Move Instructions 5-33• Indirect addresses are not allowed. A burst of data is fetched fromthe source address, put into the DMA FIFO and then w

5-34 SCSI SCRIPTS Instruction Set5.7.2 Read/Write System Memory from SCRIPTSBy using the Memory Move instruction, single or multiple register valuesar

Load and Store Instructions 5-355.7.4 Third DwordTEMP Register [31:0]These bits contain the destination address for theMemory Move.5.8 Load and Store

5-36 SCSI SCRIPTS Instruction SetThe SIOM and DIOM bits in the DMA Mode (DMODE) register determinewhether the destination or source address of the ins

Load and Store Instructions 5-37Note: This bit has no effect unless the Prefetch Enable bit in theDMA Control (DCNTL) register is set.LS Load and Stor

5-38 SCSI SCRIPTS Instruction Set

LSI53C875A PCI to Ultra SCSI Controller 6-1Chapter 6ElectricalSpecificationsThis section specifies the LSI53C875A electrical and mechanicalcharacteris

2-2 Functional DescriptionFigure 2.1 LSI53C875A Block Diagram2.1 PCI Functional DescriptionThe LSI53C875A implements a PCI-to-Wide Ultra SCSI controll

6-2 Electrical SpecificationsTable 6.1 Absolute Maximum Stress Ratings11. Stresses beyond those listed above may cause permanent damage to the device.

DC Characteristics 6-3Table 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/Symbol Parameter Min Max Unit Test ConditionsVIHInput high

6-4 Electrical SpecificationsTable 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/,DEVSEL/,STOP/,PERR/,PARSymbol Parameter Min Ma

TolerANT Technology Electrical Characteristics 6-56.2 TolerANT Technology Electrical CharacteristicsThe LSI53C875A features TolerANT technology, which

6-6 Electrical SpecificationsTable 6.11 TolerANT Technology Electrical Characteristics for SE SCSI SignalsSymbol Parameter Min11. These values are gua

TolerANT Technology Electrical Characteristics 6-7Figure 6.1 Rise and Fall Time Test ConditionFigure 6.2 SCSI Input FilteringFigure 6.3 Hysteresis of

6-8 Electrical SpecificationsFigure 6.4 Input Current as a Function of Input VoltageFigure 6.5 Output Current as a Function of Output Voltage+40+200−2

AC Characteristics 6-96.3 AC CharacteristicsThe AC characteristics described in this section apply over the entirerange of operating conditions (refer

6-10 Electrical SpecificationsTable 6.1 3 and Figure 6.7 provide Reset Input timing data.Figure 6.7 Reset InputTable 6.1 4 and Figure 6.8 provide Inte

PCI and External Memory Interface Timing Diagrams 6-11Figure 6.8 Interrupt Output6.4 PCI and External Memory Interface Timing DiagramsFigure 6.9 throu

PCI Functional Description 2-32.1.1.1 Configuration SpaceThe host processor uses the PCI configuration space to initialize theLSI53C875A through a def

6-12 Electrical Specifications– Burst Read, 32-Bit Address and Data– Burst Read, 64-Bit Address and Data– Burst Write, 32-Bit Address and Data– Burst

PCI and External Memory Interface Timing Diagrams 6-136.4.1 Target TimingThe tables and figures in this section describe target timings.Figure 6.9 PCI

6-14 Electrical SpecificationsFigure 6.10 PCI Configuration Register WriteTable 6.16 PCI Configuration Register WriteSymbol Parameter Min Max Unitt1Sh

PCI and External Memory Interface Timing Diagrams 6-15Figure 6.11 32-Bit Operating Register/SCRIPTS RAM ReadTable 6.17 32-Bit Operating Register/SCRIP

6-16 Electrical SpecificationsFigure 6.12 64-Bit Address Operating Register/SCRIPTS RAM ReadTable 6.18 64-Bit Address Operating Register/SCRIPTS RAM R

PCI and External Memory Interface Timing Diagrams 6-17Figure 6.13 32-Bit Operating Register/SCRIPTS RAM WriteTable 6.19 32-Bit Operating Register/SCRI

6-18 Electrical SpecificationsFigure 6.14 64-Bit Address Operating Register/SCRIPTS RAM WriteTable 6.20 64-Bit Address Operating Register/SCRIPTS RAM

PCI and External Memory Interface Timing Diagrams 6-196.4.2 Initiator TimingThe tables and figures in this section describe LSI53C875A initiatortiming

6-20 Electrical SpecificationsFigure 6.15 Nonburst Opcode Fetch, 32-Bit Address and DataCLK(Driven by System)FRAME/(Driven by LSI53C875A)AD(Driven by

PCI and External Memory Interface Timing Diagrams 6-21Table 6.22 Burst Opcode Fetch, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared sign

2-4 Functional Description2.1.2.1 Interrupt Acknowledge CommandThe LSI53C875A does not respond to this command as a slave and itnever generates this c

6-22 Electrical SpecificationsFigure 6.16 Burst Opcode Fetch, 32-Bit Address and DataCLK(Driven by System)FRAME/(Driven by LSI53C875A)AD(Driven by LSI

PCI and External Memory Interface Timing Diagrams 6-23Table 6.23 Back-to-Back Read, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signa

6-24 Electrical SpecificationsFigure 6.17 Back-to-Back Read, 32-Bit Address and DataCLK(Driven by System)FRAME/(Driven by LSI53C875A)AD(Driven by LSI5

PCI and External Memory Interface Timing Diagrams 6-25Table 6.24 Back-to-Back Write, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared sign

6-26 Electrical SpecificationsFigure 6.18 Back-to-Back Write, 32-Bit Address and DataCLK(Driven by System)FRAME/(Driven by LSI53C875A)AD(Driven by LSI

PCI and External Memory Interface Timing Diagrams 6-27Table 6.25 Burst Read, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input

6-28 Electrical SpecificationsFigure 6.19 Burst Read, 32-Bit Address and Datat1t2CLKGPIO0_FETCH/(Driven by LSI53C875A)GPIO1_MASTER/(Driven by LSI53C87

PCI and External Memory Interface Timing Diagrams 6-29Table 6.26 Burst Read, 64-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input

6-30 Electrical SpecificationsFigure 6.20 Burst Read, 64-Bit Address and Datat1t2CLKGPIO0_FETCH/(Driven by LSI53C875A)GPIO1_MASTER/(Driven by LSI53C87

PCI and External Memory Interface Timing Diagrams 6-31Table 6.27 Burst Write, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal inpu

PCI Functional Description 2-52.1.2.3 I/O Read CommandThe I/O Read command reads data from an agent mapped in I/Oaddress space. All 32 address bits ar

6-32 Electrical SpecificationsFigure 6.21 Burst Write, 32-Bit Address and Datat1CLK(Driven by System)GPIO0_FETCH/(Driven by LSI53C875A)GPIO1_MASTER/(D

PCI and External Memory Interface Timing Diagrams 6-33Table 6.28 Burst Write, 64-Bit Address and 32-Bit DataSymbol Parameter Min Max Unitt1Shared sign

6-34 Electrical SpecificationsFigure 6.22 Burst Write, 64-Bit Address and 32-Bit Datat1CLK(Driven by System)GPIO0_FETCH/(Driven by LSI53C875A)GPIO1_MA

PCI and External Memory Interface Timing Diagrams 6-356.4.3 External Memory TimingThe tables and figures in this section describe LSI53C875A externalt

6-36 Electrical SpecificationsFigure 6.23 External Memory Read12 3 4 56 7 8 9CLK(Driven by System)PA R(Driven by Master-Addr;IRDY/(Driven by Master)TR

PCI and External Memory Interface Timing Diagrams 6-37Figure 6.23 External Memory Read (Cont.)MAD(Addr driven by LSI53C875A;Data driven by Memory)11 1

6-38 Electrical SpecificationsTable 6.30 External Memory WriteSymbol Parameter Min Max Unitt1Shared signal input setup time 7 – nst2Shared signal inpu

PCI and External Memory Interface Timing Diagrams 6-39The External Memory Write timings start on page 6-40.

6-40 Electrical SpecificationsFigure 6.24 External Memory Write12 34 5 6 78 9CLK(Driven by System)PA R(Driven by Master-Addr;IRDY/(Driven by Master)TR

PCI and External Memory Interface Timing Diagrams 6-41Figure 6.24 External Memory Write (Cont.)MAD(Addr driven by LSI53C875A;Data driven by Memory)11

2-6 Functional Description2.1.2.10 Memory Read Multiple CommandThis command is identical to the Memory Read command except that itadditionally indicat

6-42 Electrical SpecificationsFigure 6.25 Normal/Fast Memory (≥= 128 Kbytes) Single Byte Access Read CycleTable 6.31 Normal/Fast Memory (≥= 128 Kbytes

PCI and External Memory Interface Timing Diagrams 6-43Figure 6.26 Normal/Fast Memory (≥= 128 Kbytes) Single Byte Access Write CycleTable 6.32 Normal/F

6-44 Electrical SpecificationsFigure 6.27 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Read CycleMAD(Addr Driven by LSI53C875A;MAS1/(Driven

PCI and External Memory Interface Timing Diagrams 6-45Figure 6.27 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Read Cycle(Cont.)MAD(Addr Dr

6-46 Electrical SpecificationsFigure 6.28 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Write CycleMAD(Driven by LSI53C875A)MAS1/(Driven by

PCI and External Memory Interface Timing Diagrams 6-47Figure 6.28 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Write Cycle(Cont.)MAD(Driven

6-48 Electrical SpecificationsFigure 6.29 Slow Memory (≤= 128 Kbytes) Read CycleTable 6.33 Slow Memory (≤= 128 Kbytes) Read CycleSymbol Parameter Min

PCI and External Memory Interface Timing Diagrams 6-49Figure 6.30 Slow Memory (≤= 128 Kbytes) Write CycleTable 6.34 Slow Memory (≤ 128 Kbytes) Write C

6-50 Electrical SpecificationsFigure 6.31 ≤ 64 Kbytes ROM Read CycleTable 6.35≤= 64 Kbytes ROM Read CycleSymbol Parameter Min Max Unitt11Address setup

PCI and External Memory Interface Timing Diagrams 6-51Figure 6.32 ≤ 64 Kbyte ROM Write CycleTable 6.36≤= 64 Kbyte ROM Write CycleSymbol Parameter Min

PCI Functional Description 2-7line. This command is intended for use with bulk sequential data transferswhere the memory system and the requesting mas

6-52 Electrical Specifications6.5 SCSI Timing DiagramsThe tables and diagrams in this section describe the LSI53C875A SCSItimings.Figure 6.33 Initiato

SCSI Timing Diagrams 6-53Figure 6.34 Initiator Asynchronous ReceiveTable 6.38 Initiator Asynchronous ReceiveSymbol Parameter Min Max Unitt1SACK/ asser

6-54 Electrical SpecificationsFigure 6.35 Target Asynchronous SendTable 6.39 Target Asynchronous SendSymbol Parameter Min Max Unitt1SREQ/ deasserted f

SCSI Timing Diagrams 6-55Figure 6.36 Target Asynchronous ReceiveTable 6.40 Target Asynchronous ReceiveSymbol Parameter Min Max Unitt1SREQ/ deasserted

6-56 Electrical SpecificationsTable 6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes(16-Bit Transfers) 40 MHz ClockSymbol Param

SCSI Timing Diagrams 6-57Figure 6.37 Initiator and Target Synchronous TransferSREQ/or SACK/Send DataSD[15:0]/, SDP[1:0]/Receive DataSD[15:0]/,SDP[1:0]

6-58 Electrical Specifications6.6 Package DiagramsThis section of the manual has a package drawing and pinout for boththe PQFP and BGA.Figure 6.38 LSI

Package Diagrams 6-59Figure 6.38 160-pin PQFP (P3) Mechanical Drawing (Sheet 2 of 2)Important: This drawing may not be the latest version. For board l

6-60 Electrical SpecificationsTable 6.44 160 PQFP Pin List by LocationNC 121NC 122VSSIO 123NC 124NC 125TEST_HSC/ 126TEST_RST/ 127VDDIO 128VDDA 129TCK

Package Diagrams 6-61Figure 6.39 169-Pin BGA Mechanical DrawingImportant: This drawing may not be the latest version. For board layout and manufacturi

Preface iiiPrefaceThis book is the primary reference and technical manual for theLSI53C875A PCI to Ultra SCSI Controller. It contains a completefuncti

2-8 Functional Description2.1.2.13 Memory Write and Invalidate CommandThe Memory Write and Invalidate command is identical to the MemoryWrite command,

6-62 Electrical SpecificationsTable 6.45 169 BGA Pin List by LocationVSSIO K12SIO K13PCI_AD[9] L1PCI_AD[8] L2PCI_AD[4] L3PCI_AD[2] L4VDDCORE L5VSSCORE

LSI53C875A PCI to Ultra SCSI Controller A-1Appendix ARegister SummaryTable A.1 LSI53C875A PCI Register MapRegister Name Address Read/Write PageBase Ad

A-2 Register SummaryPower Management Capabilities (PMC) 0x42–0x43 Read Only 4-15Power Management Control/Status (PMCSR) 0x44–0x45 Read/Write 4-16Reser

Register Summary A-3DMA Command (DCMD) 0x27 Read/Write 4-63DMA Control (DCNTL) 0x3B Read/Write 4-70DMA FIFO (DFIFO) 0x20 Read/Write 4-57DMA Interrupt

A-4 Register SummaryRemaining Byte Count (RBC) 0xC8–0xCB Read/Write 4-105Reserved 0x53 – 4-94Reserved 0x5A–0x5B – 4-99Reserved 0xBC–0xBF – 4-103Reserv

Register Summary A-5SCSI Interrupt Enable Zero (SIEN0) 0x40 Read/Write 4-73SCSI Interrupt Status One (SIST1) 0x43 Read Only 4-78SCSI Interrupt Status

A-6 Register Summary

LSI53C875A PCI to Ultra SCSI Controller B-1Appendix BExternal MemoryInterface DiagramExamplesAppendix B has example external memory interface diagrams

B-2 External Memory Interface Diagram ExamplesFigure B.2 64 Kbyte Interface with 150 ns MemoryLSI53C875A27C512-15/MOE/OEMCE/CED08MAD[7:0]BusCKQ08A[7:0

External Memory Interface Diagram Examples B-3Figure B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 nsMemoryLSI53C875A27C020-15

PCI Functional Description 2-9After each data transfer, the chip re-evaluates the burst size based onthe amount of remaining data to transfer and agai

B-4 External Memory Interface Diagram ExamplesFigure B.4 512 Kbyte Interface with 150 ns MemoryOEWED[7:0]A0A16...LSI53C875AMOE/8MAD[7:0]BusA[7:0]D0CKQ

LSI53C875A PCI to Ultra SCSI Controller IX-1IndexSymbols(64TIMOD) 4-97(A7) 5-23(AAP) 4-22(ABRT) 4-40, 4-48(ACK) 4-37, 4-39(ADB) 4-23(ADCK) 4-60(ADDER)

IX-2 Index(ERBA) 4-12(ERL) 4-67(ERMP) 4-68(ESA) 4-106(EWS) 4-29(EXC) 4-23(EXT) 4-90(FBL3) 4-59(FE) 4-82(FF[3:0]) 4-43(FF4) 4-46(FFL) 4-53(FLF) 4-56(FL

Index IX-3(SGE) 4-74, 4-77(SI) 4-51(SID) 4-11(SIEN0) 4-73(SIEN1) 4-75(SIGP) 4-49, 4-54(SIOM) 4-67(SIP) 4-50(SIR) 4-40(SIST0) 4-76(SIST1) 4-78(SLB) 4-8

IX-4 Indexburst (Cont.)length (BL[1:0]) 4-66length bit 2 (BL2) 4-61opcode fetch enable (BOF) 4-68size selection 2-6buscommand and byte enables 3-5faul

Index IX-5DMAinterrupt (Cont.)pending (DIP) 4-50mode (DMODE) 4-66SCRIPTSpointer (DSP) 4-64pointer save (DSPS) 4-65status (DSTAT) 4-39DMA nextaddress (

IX-6 IndexIDSEL 2-3, 3-6signal 2-5illegal instruction detected (IID) 4-40, 4-69immediatearbitration (IARB) 4-24data 5-23indirect addressing 5-6initial

Index IX-7memory (Cont.)read line command 2-6read multiple 2-10, 2-11read multiple command 2-6space 2-2, 2-3to memory 2-16to memory moves 2-16write 2-

IX-8 Indexreset 3-4input 6-10SCSI offset (ROF) 4-89response ID one (RESPID1) 4-86response ID zero (RESPID0) 4-86return instruction 5-27revision ID (RI

Index IX-9SEL 2-39select 2-17instruction 5-16with ATN/ 5-20with SATN/ on a start sequence (WATN) 4-22selected (SEL) 4-74, 4-77selection or reselection

2-10 Functional Descriptionsoftware enabled or disabled to allow the user full flexibility in using thesecommands.2.1.3.1 Enabling Cache ModeIn order

IX-10 IndexUltra SCSI (Cont.)single-ended transfers20.0 Mbytes (16-bit transfers)quadrupled 40 MHz clock 6-5620.0 Mbytes (8-bit transfers)40 MHz clock

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PCI Functional Description 2-11• To issue Memory Read Multiple commands, the Read Multipleenable bit in the DMA Mode (DMODE) register must be set.• To

2-12 Functional Description• Multiple Memory Write and Invalidates.• A single data residual Memory Write to complete the transfer.Table 2.2 describes

PCI Functional Description 2-132.1.3.5 Examples:MR = Memory Read, MRL = Memory Read Line, MRM = Memory ReadMultiple, MW = Memory Write, MWI = Memory W

2-14 Functional DescriptionRead Example 3 –Burst = 16 Dwords, Cache Line Size = 8 Dwords:Write Example 1 –Burst=4Dwords,CacheLineSize=4Dwords:CtoE: MR

PCI Functional Description 2-15Write Example 2 –Burst=8Dwords,CacheLineSize=4Dwords:DtoF: MW (15 bytes)MWI (16 bytes)MW (1 byte)AtoH: MW (15 bytes)MWI

2-16 Functional DescriptionWrite Example 3 –Burst = 16 Dwords, Cache Line Size = 8 Dwords:2.1.3.6 Memory-to-Memory MovesMemory-to-Memory Moves also su

SCSI Functional Description 2-17accessed as a register-oriented device. Error recovery and/or diagnosticprocedures use the ability to sample and/or as

iv Preface• Chapter 6, Electrical Specifications contains the electricalcharacteristics and AC timing diagrams.• Appendix A, Register Summary is a reg

2-18 Functional DescriptionThe Phase Mismatch Jump logic powers up disabled and must beenabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, b

SCSI Functional Description 2-192.2.3 64-Bit Addressing in SCRIPTSThe LSI53C875A has a 32-bit PCI interface which provides 64-bitaddress capability in

2-20 Functional Description2.2.5 Designing an Ultra SCSI SystemSince Ultra SCSI is based on existing SCSI standards, it can use existingdriver program

SCSI Functional Description 2-21Step3. HalttheSCSIclockbysettingtheHaltSCSIClockbit(SCSITest Three (STEST3),bit5).Step 4. Set the clock conversion fac

2-22 Functional Description• On every Store instruction. The Store instruction may also be usedto place modified code directly into memory. To avoid i

SCSI Functional Description 2-23Load and Store instructions, refer to Chapter 5, “SCSI SCRIPTSInstruction Set.”2.2.9 JTAG Boundary Scan TestingThe LSI

2-24 Functional Description2.2.11 Parity OptionsThe LSI53C875A implements a flexible parity scheme that allows controlof the parity sense, allows pari

SCSI Functional Description 2-25Table 2.3 Bits Used for Parity Control and GenerationBit Name Location DescriptionAssert SATN/ onParity ErrorsSCSI Con

2-26 Functional DescriptionTable 2.4 SCSI Parity ControlEPC11. EPC = Enable Parity Checking (bit 3 SCSI Control Zero (SCNTL0)).ASEP22. ASEP = Assert S

SCSI Functional Description 2-27Figure 2.2 Parity Checking/Generation2.2.12 DMA FIFOThe DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO i

Preface vPCI Special Interest Group2575 N.E. KatherineHillsboro, OR 97214(800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344Conventions

2-28 Functional DescriptionFigure 2.3 DMA FIFO SectionsThe LSI53C875A automatically supports misaligned DMA transfers. A944-byte FIFO allows the LSI53

SCSI Functional Description 2-29Figure 2.4 LSI53C875A Host Interface SCSI Data PathsThe following steps determine if any bytes remain in the data path

2-30 Functional Descriptionbits of the DBC register from the 10-bit value of the DMA FIFOByte Offset Counter, which consists of bits [1:0] in the CTES

SCSI Functional Description 2-31then the least significant byte or the most significant byte in theSODR register is full, respectively.Asynchronous SC

2-32 Functional DescriptionAND the result with 0x3FF for a byte count between zero and944.Step 2. Read the SCSI Status One (SSTAT1) register and exami

SCSI Functional Description 2-33Figure 2.5 Regulated Termination for Ultra SCSI2.2.14 Select/Reselect During Selection/ReselectionIn multithreaded SCS

2-34 Functional Descriptionsituation may occur when a SCSI controller (operating in the initiatormode) tries to select a target and is reselected by a

SCSI Functional Description 2-35Figure 2.6 Determining the Synchronous Transfer RateSCLKClockQuadruplerQCLKSCFDividerCCFDividerSynchronousDividerAsync

2-36 Functional Description2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])The SCF[2:0] bits select the factor by which the freque

SCSI Functional Description 2-37• Ultra SCSI Enable bit, SCSI Control Three (SCNTL3) register bit 7.Setting this bit enables Ultra SCSI synchronous tr

vi Preface

2-38 Functional Descriptionpolled when polled interrupts are used. It is also the first register thatshould be read after the IRQ/ pin is asserted in

SCSI Functional Description 2-39conditions caused the DMA-type interrupt, and clears that DMA interruptcondition. Bit 7 in DSTAT, DFE, is purely a sta

2-40 Functional DescriptionPurpose Timer Expired (GEN), and Handshake-to-Handshake TimerExpired (HTH) interrupts are nonfatal.When operating in the Ta

SCSI Functional Description 2-41Interrupts can be disabled by setting SYNC_IRQD bit 0 in the InterruptStatus One (ISTAT1) register. If an interrupt is

2-42 Functional Descriptiongenerates an interrupt, the bit corresponding to the earlier maskednonfatal interrupt is still set.A related situation to i

SCSI Functional Description 2-43• If the instruction is a JUMP/CALL WHEN/IF <phase>, the DMASCRIPTS Pointer (DSP) is updated to the transfer add

2-44 Functional Description2.2.17 Chained Block MovesSince the LSI53C875A has the capability to transfer 16-bit wide SCSIdata, a unique situation occu

SCSI Functional Description 2-45Figure 2.7 Block Move and Chained Block Move Instructions2.2.17.1 Wide SCSI Send BitThe WSS bit is set whenever the SC

2-46 Functional Descriptiontwo bytes are sent out across the bus, regardless of the type of BlockMove instruction (normal or chained). The flag is aut

SCSI Functional Description 2-472.2.17.5 Chained Block Move SCRIPTS InstructionA chained Block Move SCRIPTS instruction is primarily used to transferc

Contents viiContentsChapter 1 General Description1.1 New Features in the LSI53C875A 1-31.2 Benefits of Ultra SCSI 1-31.3 TolerANT®Techn ology 1-41.4 L

2-48 Functional Descriptionsend command, the first byte of the data send command is assumed tobe the high-order byte and is “married” with the low-ord

Parallel ROM Interface 2-49The LSI53C875A supports a variety of sizes and speeds of expansionROM, using pull-down resistors on the MAD[3:0] pins. The

2-50 Functional Description2.4 Serial EEPROM InterfaceThe LSI53C875A implements an interface that allows attachment of aserial EEPROM device to the GP

Power Management 2-512.4.2 No Download ModeWhen MAD7 is pulled up through an external resistor, the automaticdownload is disabled and no data is autom

2-52 Functional DescriptionThe LSI53C875A power states shown in Table 2. 8 are independentlycontrolled through two power state bits that are located i

Power Management 2-532.5.3 Power State D2Power state D2 is a lower power state than D1. In this state theLSI53C875A core is placed in the coma mode. T

2-54 Functional Description

LSI53C875A PCI to Ultra SCSI Controller 3-1Chapter 3Signal DescriptionsThis chapter presents the LSI53C875A pin configuration and signaldefinitions us

3-2 Signal Descriptions3.1 LSI53C875A Functional Signal GroupingFigure 3.1 presents the LSI53C875A signals by functional group.Figure 3.1 LSI53C875A F

Signal Descriptions 3-33.2 Signal DescriptionsThe Signal Descriptions are divided into PCI Bus Interface Signals, SCSIBus Interface Signals, GPIO Sign

viii Contents2.2.11 Parity Options 2-242.2.12 DMA FIFO 2-272.2.13 SCSI Bus Interface 2-322.2.14 Select/Reselect During Selection/Reselection 2-332.2.1

3-4 Signal Descriptions3.3 PCI Bus Interface SignalsThe PCI Bus Interface Signals section contains tables describing thesignals for the following sign

PCI Bus Interface Signals 3-53.3.2 Address and Data SignalsTable 3.3 describes Address and Data signals.Table 3.3 Address and Data SignalsName PQFP BG

3-6 Signal Descriptions3.3.3 Interface Control SignalsTable 3.4 describes the Interface Control signals.Table 3.4 Interface Control SignalsName PQFP B

PCI Bus Interface Signals 3-73.3.4 Arbitration SignalsTable 3.5 describes Arbitration signals.3.3.5 Error Reporting SignalsTable 3.6 describes the Err

3-8 Signal Descriptions3.3.6 Interrupt SignalTable 3.7 describes the Interrupt signal.3.4 SCSI Bus Interface SignalsThe SCSI Bus Interface signals sec

SCSI Bus Interface Signals 3-93.4.2 SCSI SignalsTable 3.9 describes the SCSI signals.3.4.3 SCSI Control SignalsTable 3.1 0 describes the SCSI Control

3-10 Signal Descriptions3.5 GPIO SignalsTable 3.1 1 describes the SCSI GPIO signals.Table 3.11 GPIO SignalsName PQFP BGA Type Strength DescriptionGPIO

ROM Flash and Memory Interface Signals 3-113.6 ROM Flash and Memory Interface SignalsTable 3.1 2 describes the ROM Flash and Memory Interface signals.

3-12 Signal Descriptions3.7 Test Interface SignalsTable 3.1 3 describes Test Interface signals.MAD[7:0] 59–62,64–67L7, M7,N7, K7,M8, N8,L8, K8I/O 4 mA

Power and Ground Signals 3-133.8 Power and Ground SignalsTable 3.1 4 describes the Power and Ground signals.Table 3.14 Power and Ground SignalsName PQ

Contents ixChapter 4 Registers4.1 PCI Configuration Registers 4-14.2 SCSI Registers 4-184.3 64-Bit SCRIPTS Selectors 4-994.4 Phase Mismatch Jump Regis

3-14 Signal Descriptions3.9 MAD Bus ProgrammingThe MAD[7:0] pins, in addition to serving as the address/data bus for thelocal memory interface, also a

MAD Bus Programming 3-15• The MAD[0] pin is the slow ROM pin. When pulled up, it enables twoextra cycles of data access time to allow use of slower me

3-16 Signal Descriptions

LSI53C875A PCI to Ultra SCSI Controller 4-1Chapter 4RegistersThis chapter describes all LSI53C875A registers and is divided into thefollowing sections

4-2 Registersbits that are currently supported by the LSI53C875A are described in thischapter. Reserved bits should not be accessed.Registers:0x00–0x0

PCI Configuration Registers 4-3Registers:0x02–0x03Device IDRead OnlyDID Device ID [15:0]This 16-bit register identifies the particular device. TheLSI5

4-4 RegistersR Reserved 5WIE Write and Invalidate Enable 4This bit allows the LSI53C875A to generate write andinvalidate commands on the PCI bus. The

PCI Configuration Registers 4-5Registers:0x06–0x07StatusRead/WriteReads to this register behave normally. Writes are slightly different in thatbits ca

4-6 RegistersThese bits are read only and should indicate the slowesttime that a device asserts DEVSEL/ for any buscommand except Configuration Read a

PCI Configuration Registers 4-7Registers:0x09–0x0BClass CodeRead OnlyCC Class Code [23:0]This 24-bit register is used to identify the generic function